OH2NLT Experimental Digital HF transmitter
25.11.2007
OH2NLT fully digital station
Left Digital RX, middle Digital TX and right 50W PA
Today’s large FPGA chips and VHDL language together is a powerful tool. With this combination you can do almost anything your imagination invents. I decided to learn VHDL language. Learning by doing is convenient way for me to learn new things. Next I had to find sensible project to try. In the summer of 2006 I made an
Digital HF receiver with DSP processor. Since project I have been thinking about doing a digital TX. Digital TX is a quite large effort for first project but I decided to give a try. Now about one month later I have working prototype of my own Digital TX. My test platform is Altera DE1 board with Cyclone II EP2C20F486 FPGA and Texas Instruments DAC5672 DCA board.Short presentation of the project
Block diagram of the digital TX.
Large PDF version.RF sample rate is 50 MHz. Audio sample rate is sensible to be "low" around 8khz. Low sample rate makes it easier to implement audio filters and Hilbert transformer. I chose 50MHz / 6144 = 8138,0208Hz. Interpolating with factor of 6144 showed to be difficult task. First I tried Altera Megafunction CIC interpolator but did not get it work. Input sample rate was always too slow by factor of three. I started to do what I first thought to be impossible, my own CIC interpolator filter. Literature and the Internet is full of very good theory about the subject, but I did not find a single VHDL code example. I managed to get my filter working with some Visual Basic simulations and adding enough bits to every integrator stage. According the theory 6144 CIC interpolator gain is over 220dB. This is the difficult part to handle in the VHDL code.
Some history and highlights of the project
In fact
my first try was already in the summer of 2007 with Xilinx XC3S100E chip and Ti DAC2902 12-bit DAC. VHDL code was Xilinx Logi Core NCO and own SPI interface to set frequency with external micro controller. Everything worked fine. Because of other summer activities and lack of Xilinx board I/O I left the project was dormant.
October 2007 I got Altera DE1 evaluation board. This board contains enough I/O and support chips for digital TX implementation.
I connected my Ti DAC 2902 board to the Altera DE1 board. Again first try was Altera Megafunction NCO. Unpleasant surprise was that Altera Megafunction NCO IP block and all the filter blocks are licensed code. In the Xilinx ISE these are free. With DE1 board connected to the PC you can however run evaluation versions. My VHDL learning however started. I did drivers for the 7-segment display on the DE1 board. Adapted Open Cores UART for PC control connection. Altera board demo code is written in Verilog so I had to write audio codec drivers also. I used ready Altera Verilog code for codec I2C communications.
Middle of November
I switched the DAC to 14-bit Texas Instruments DAC5672 chip/board. VHDL learning continued with FIR filters and CIC interpolator code. First signs of life were already noticeable.First cross band QSO was held with OH7TE 20.11.2007. Frequency setup is done from PC with Visual Basic application.
Digital station needed more power. Quick and dirty 50W PA was build "over night".
Boards mounted on aluminum plate for easier handling. TR switch added to the PA board. I also wrote my own NCO block to get rid of Altera evaluation NCO and compulsory USB PC connection. Now my application is loaded from DE1 board configuration memory. Now all blocks are also portable to other environments.
My very first Digital TX VHDL code. Comments are welcome.
Some measurements
3.7 MHz Carrier wave straight from DAC output(5Mhz / div). Same as scope picture. I was surprised how clean signal DAC5672 and my NCO code produces.
3.7 MHz Carrier wave after RF LPF.
Overflow in the digital system is catastrophe. Same output as before but too large audio input level cause overflow. Same as scope picture. I need to do some work to prevent overload conditions. Most probably problem is in my CIC filter.
CW keying tests with sin(x)/X on/off slope
I added some code to my old Digital RX . Now The TX NCO tracks RX tuning. Conversion calculations are needed before frequency data is transmitted to the TX board. RX NCO clock is 32,768MHz and TX NCO clock is 50MHz.
Receiver and Altera board are connected together via RS232 ports.Some www links.
